Semiconductor integrated circuits contain many distinct electronic devices having conductive elements as part of the device structure. In order to operate as a circuit, each device needs to be electrically interconnected with other devices. Interconnection occurs during the fabrication process by forming an intricate network of conductive material in contact with certain elements of the devices.
For example, part of a semiconductor integrated circuit may be made up of hundreds of discrete field effect transistors having interconnected gate electrodes. The typical structure of this device is shown in FIG. 1. Here, a single crystal silicon substrate 1 has doped regions forming the source 2 and drain 3 of a transistor. The gate electrode 4 is formed by a layer of conductive polycrystalline silicon (polysilicon or simply "poly") above an insulating gate oxide layer 5. Although less conductive, polysilicon has advantages over conductive metals, since it allows for lower threshold voltages and higher density of cells. Since it has a moderately low sheet resistivity, the polysilicon layer can be extended to adjacent devices, providing interconnection as shown in FIG. 2. Each device 6 has its gate formed by the extended polysilicon region 7 which forms a ridge above the planar substrate. Similarly, memory devices using structures such as stacked capacitors use polysilicon in forming their plate regions and in interconnecting adjacent devices.
Although polysilicon has low sheet resistivity, it still has limitations. Interconnect lines made of poly must have a relatively large cross-section to be conductive enough to operate effectively. This in turn increases the size of the overall integrated circuit, reducing speed and flexibility while increasing cost.
The long thin poly lines interconnecting an array of memory devices are driven by row driver circuits. The maximum length of line handled by a single driver is determined by the time it takes for signals to travel down the line--the RC time constant. When the time gets too long, more row drivers must be added in parallel to reduce the total resistance, increasing overall chip size. Conversely, less drivers are needed when the interconnect lines are more conductive.
If conductivity were the only design criterion, silver or aluminum would be the material of choice to form device interconnections. However, many of the processes required in fabricating semiconductor integrated circuits use high heat. Both of these metals have relatively low melting points subjecting them and surrounding material to corruption during subsequent fabrication steps. Their relatively high coefficients of thermal expansion compared to materials such as silicon and silicon dioxide used in the fabrication of other microcircuit elements can cause stress, warping and separation as the metals expand and retract over such materials. Other usefully conductive metals such as gold and copper rapidly diffuse through the substrate forming generation sites, thereby reducing minority carrier lifetime and degrading refresh performance in memory devices.
Currently, the methods and structures used for decreasing the sheet resistivity of polysilicon involve tungsten and titanium which although less conductive than silver, have a much higher melting point and smaller coefficient of thermal expansion. FIG. 3 shows one such method where a layer of tungsten silicide 8 (WSi.sub.x, where X is any integer greater than or equal to 1, but most commonly 2 or 3 when used in integrated circuits) has been deposited atop the poly layer 9. Common methods for depositing WSi.sub.x are physical vapor deposition (PVD or sputtering) and chemical vapor deposition (CVD). This resulting combination of layers is called WSi.sub.x polycide. The minimum sheet resistance for WSi.sub.x polycide is about 5-10 ohms per square.
Using titanium instead of tungsten provides greater conductivity, however, other problems arise. Titanium silicide (TiSi.sub.x) is formed by first depositing a layer titanium atop the poly, then heating it. The resulting titanium silicide layer can suffer from severe aglomeration problems if the TiSi.sub.x layer is exposed to temperatures greater than 850.degree. C. Since many fabrication processes require high heat, the use of TiSi.sub.x becomes restricted. For example, stacked capacitor DRAM processes require deposition of the titanium after the first poly deposition, with many processes left to be performed. Other problems with using TiSi.sub.x include unwanted dopant segregation and diffusion of titanium down through the poly into the substrate during heating which can reduce minority carrier lifetime during operation. In addition, etching TiSi.sub.x is difficult because the layer created is very rough, having non-uniform thickness. This makes it difficult to stop etching the TiSi.sub.x without penetrating into the underlying poly layer. If the titanium is etched prior to its conversion into TiSi.sub.x, the volume change due to thermal exansion and contraction which occurs during conversion may cause cracks or voids to form.
It is desirable therefore, to have a structure which increases the conductivity of device elements and interconnections without the drawbacks descibed above.